HRL Laboratories is developing an advanced cooling system for stacked microelectronic chips through the PHARINHEITS program, aiming to exceed DARPA’s thermal transfer goals. The project uses 3D Heterogeneous Integration (3DHI) to address high heat density challenges, enabling next-gen radar and communication systems. In collaboration with top universities, HRL aims to improve thermal management and system performance in areas like RF systems, AI, and image analysis. Initial data was presented at the GOMACtech conference in Pasadena. They write:
Source: HRL Laboratories
HRL Laboratories plans to surpass heat transfer metrics set out by the Defense Advanced Research Project Agency (DARPA) with a novel cooling system for stacks of microelectronic chips. The program, called PHased ARray with INnovative HEterogeneously Integrated Thermal Solution (PHARINHEITS), aims to create compact thermal management technology in a chip stack using 3D Heterogeneous Integration (3DHI). […]
By partnering with premier university labs, HRL is uniting experts in heat transfer technologies, Si CMOS, GaN, heterogeneous integration and RF front-ends.
University of Maryland is focusing on high-performance bottom-of-stack microchannel thermal technology development and compact, additively manufactured heat exchanger fabrication under the leadership of Professor Michael Ohadi
Stanford University is focusing on multifunctional top-of-stack microchannel thermal technology development under the leadership of Adjunct Professor Mehdi Asheghi and Professor Ken Goodson
Purdue University is focusing on reliability engineering and thermomechanical modeling under the leadership of Professors Ganesh Subbarayan and Shubhra Bansal
MIT Lincoln Laboratory is focusing on silicon chip design and fabrication under the leadership of Doctors Chenson Chen and Ryan Keech
HRL is directing the overall program, leading the system design, developing thermal isolation and thermal spreading techniques, leading the 3D integration, and executing system performance testing. “HRL’s experience in 3D integration is crucial to the disparate chips and cooling systems working together in a tightly coupled package,” said Christopher Roper, principal investigator at HRL.
“The challenge in cooling this 3DHI stack of chips is local heat density,” Roper continued. “We need to cool the heat equivalent of more than 190 laptop CPUs, but in the size of a single CPU package.”
By surpassing current integrated thermal management limits, the PHARINHEITS program will enable next-generation millimeter-wave (mm wave) radio frequency phased arrays with dramatically increased transmit power relative to current systems. These stacked chips may be used in future phased array radar and communication systems with increased range.
Inadequate integrated thermal management limits continued maturation of compact high-performance microsystems. 3DHI chip stacks, for example, are more compact, which allows for faster, smaller and lighter phased arrays. However, the challenge has traditionally been how to disperse the heat that they generate because the thicker die stack with its additional internal thermal interfaces inhibits heat flow. This challenge limits growth in system capabilities (particularly in radio frequency systems, image analysis, and high-performance computing, including artificial intelligence and machine learning applications) in size, weight, and power (SWaP) constrained applications. Recently DARPA set forth a set of metrics around how much thermal dissipation is required. HRL and university partners plan to surpass these goals.
